Various aspects of both hardware and software development rely on estimation of power consumption by processors that execute machine code instructions. Power consumption estimations are important components of chip verification and validation, circuit design and software optimization, and process development.
For complex processor designs, processor behavior is sometimes modeled using electronic system level (ESL) models in which low-level hardware functions are represented by higher-level, more abstract functional blocks. The use of ESL models enables design optimization activities to be conducted at a relatively early stage in the design process.
Power estimations using ESL models are often based on executed instructions and calculated from state-level transitions. Transitions can be between active or idle states of processors and hit or miss states of cache memories. Other methods rely on more detailed analyses of processor activity. Generally, a tradeoff exists between faster, state-level estimation methods that may lack accuracy and more accurate, detail-based methods that are slower than state-level methods.
Like reference symbols in the various drawings indicate like elements.